Generally speaking, a manufacturing process of an e-fuse is the same as that of a gate of a metal-oxide semiconductor (MOS) transistor. Therefore, during the manufacturing process of an integrated circuit, the e-fuse and the gate of the MOS transistor are manufactured simultaneously.
FIGS. 1A to 1E illustrate schematic diagrams of a conventional manufacturing process of an e-fuse and a gate of a MOS transistor. Referring to FIG. 1A, an insulation layer 20 is formed on a semiconductor substrate 10. Generally, the material of the insulation layer 20 is SiO2. The left side of a dashed line is a MOS transistor region, and the right side of the dashed line is a non-MOS transistor region.
Referring to FIG. 1B, a highly doped polysilicon layer 30 is first formed on the insulation layer 20. Photo-etching is then applied to define a channel length 15 of the gate of the MOS transistor as well as drain and source regions in the MOS transistor region. Simultaneously, a position of the e-fuse is defined in the non-MOS transistor region. A first ion implantation is performed in the MOS transistor region to form a lightly doped region 16 (e.g., less than 1018 atoms/cc) on the semiconductor substrate 10. Referring to FIG. 1C, a side wall 32 is formed at the gate of the MOS transistor in the MOS transistor region. A second ion implantation is then performed to form a highly doped region 17 on the semiconductor substrate 10. Referring to FIG. 1D, the insulation layer 20 on the surface of the highly doped region 17 is removed.
Referring to FIG. 1E, a silicide layer 35 is formed in the MOS transistor region to form a source and a drain of the MOS transistor on the surface of the highly doped region 17, and the silicide layer 35 is stacked on the highly doped polysilicon layer 30 to form a metal contact point of the gate. At this stage, the silicide layer 35 is also formed in the non-MOS transistor region, and the silicide layer 35 is stacked on the highly doped polysilicon layer 30 to form a conventional e-fuse.
As mentioned above, the gate of the MOS transistor comprises the highly doped polysilicon layer 30 and the silicide layer 35 stacked on the highly doped polysilicon layer 30. During the manufacturing process of the gate, the e-fuse is formed in the non-MOS transistor region. Therefore, the e-fuse also comprises the highly doped polysilicon layer 30 and the silicide layer 35 stacked the highly doped polysilicon layer 30. Generally, the thickness of the highly doped polysilicon layer 30 is about 1K to 2K angstroms, and the resistance of the highly doped polysilicon layer 30 is about several hundred ohms per square unit. The thickness of the silicide layer 35 is about 200 to 300 angstroms, and the resistance of the silicide layer 35 is about 5 to 20 ohms per square unit.
When the e-fuse is formed, it is in a closed state. To change the e-fuse to an open state, a large current needs to flow through the e-fuse to break the e-fuse. That is, the open state of the e-fuse means that the highly doped polysilicon layer 30 and the silicide layer 35 become an open circuit. However, the e-fuse can not change from the open state to the closed state again once the e-fuse is in the open state. Moreover, when an e-fuse control circuit (not shown) is in a programming period, the e-fuse remains in the closed state or changes to the open state. When the e-fuse control circuit is in a read period, a different first level or a different second level is generated according to the open or closed state of the e-fuse.
FIGS. 2A, 2B and 2C show the closed state, the open state and a half-open state of an e-fuse, respectively. Referring to FIG. 2A, when the e-fuse is in the closed state, the highly doped polysilicon layer 30 and the silicide layer 35 are not broken by a burning procedure. Referring to FIG. 2B, when the e-fuse is in the open state, the highly doped polysilicon layer 30 and the silicide layer 35 are broken by the burning procedure.
Please refer to FIG. 2C. The resistance of the silicide layer 35 at the upper layer of the e-fuse is smaller than that of the highly doped polysilicon layer 30 at the lower layer of the e-fuse. Therefore, during the programming period, a major portion of the current flows through the silicide layer 35 at the upper layer and a minor portion of the current flows through the highly doped polysilicon layer 30 at the lower layer. Often, a circumstance that the highly doped polysilicon layer 30 is not broken by burning procedure while the silicide layer 35 is already broken occurs, as is the case shown in FIG. 2C.
When the e-fuse is changed to the half-open state after the programming period of the e-fuse control circuit, the e-fuse actually still has a resistance value of about several hundred ohms. Therefore, the e-fuse control circuit cannot correctly output the first or second level during the read period, such that the overall integrated circuit is not able to operate normally. In general, the probability of a conventional e-fuse that is in a half-open state can reach as high as 2% to 3%.
Therefore, the main object of the present disclosure is to provide an e-fuse and associated control circuit, so that the e-fuse can provide a reliable closed or open state to the control circuit with a reduced probability of being in a half-open state.